View TSC80251G1D-L12CB_7134115.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

tsc80251g1d 1 rev. c october 14, 1998 extended 8bit microcontroller with serial communication interfaces 1. description the tsc80251g1d products are derivatives of the t emic microcontroller family based on the extended 8bit c251 architecture. this family of products is tailored to 8bit microcontroller applications requiring an increased instruction throughput, a reduced operating frequency or a larger addressable memory space. the architecture can provide a significant code size reduction when compiling c programs while fully preserving the legacy of c51 assembly routines. the tsc80251g1d derivatives are pinout and software compatible with standard 80c51/fx/rx with extended onchip data memory (1 kbyte ram) and up to 256 kbytes of external code and data. additionally, the tsc83251g1d provides onchip code memory (16 kbytes rom). they provide transparent enhancements to intel's 8xc251sx family with an additional synchronous serial link controller (sslc supporting i 2 c, m wire and spi protocols), a keyboard interrupt interface and power monitoring and management features. tsc80251g1d mask rom and romless derivatives are optimized both for speed and for low power consumption on a wide voltage range. notes: this datasheet provides the technical description of the tsc80251g1d derivatives. for further information on the device usage, please request the tsc80251 programmers' guide and the tsc80251g1d design guide. for information on the eprom/otp devices, please refer to the tsc87251g1a datasheet. 2. typical applications isdn terminals highspeed modems pabx (soho) networking line cards computer peripherals printers plotters scanners banking machines barcode readers smart cards readers highend digital monitors highend joysticks purchase of temic i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
tsc80251g1d 2 rev. c october 14, 1998 3. features pinout and software compatibility with standard 80c51 products and 80c51fa/fb/ra/rb plugin replacement of intel's 80c251sx c251 core: intel's mcs 251 step d compliance 83 ns instruction cycle time @ 24 mhz 40byte register file registers accessible as bytes, words or dwords sixstage instruction pipeline 16bit internal code fetch enriched c51 instruction set 16bit and 32bit alu compare and conditional jump instructions expanded set of move instructions linear addressing 1 kbyte of onchip ram external memory space (code/data) programmable from 64 kbytes to 256 kbytes tsc83251g1d: 16 kbytes of onchip masked rom (engineering and fast production with tsc87251g1a otp/eprom version) tsc80251g1d: romless version four 8bit parallel i/o ports (ports 0, 1, 2 and 3 of the standard 80c51) serial i/o port: full duplex uart (80c51 compatible) with independent baud rate generator sslc: synchronous serial link controller i 2 c multimaster and slave protocols m wire and spi master and slave protocols three 16bit timers/counters (timers 0, 1 and 2 of the standard 80c51) ewc: event and waveform controller compatible with intel's programmable counter array (pca) common 16bit timer/counter reference with four possible clock sources (fosc/4, fosc/12, timer 1 and external input) five modules with four programmable modes: 16bit software timer/counter 16bit timer/counter capture input and software pulse measurement highspeed output and 16bit software pulse width modulation (pwm) 8bit hardware pwm without overhead 16bit watchdog timer/counter capability secure 14bit hardware watchdog timer power monitoring and management powerfail reset poweron reset (integrated on the chip) poweroff flag (cold and warm resets) software programmable system clock idle and powerdown modes keyboard interrupt interface on port 1 non maskable interrupt input (nmi) realtime wait states inputs (wait#/await#) onchip code verify with encryption for mask rom versions once mode and full speed realtime incircuit emulation support (third party vendors) high speed versions: 16 mhz and 24 mhz 5 v 10 % typical operating current: 34 ma @ 24 mhz 23 ma @ 16 mhz powerdown mode typical current 2 m a low voltage version: 2.7 v to 5.5 v 12 mhz operation typical operating current: 8 ma @ 3 v powerdown mode typical current 1 m a temperature ranges: commercial (0 c to +70 c) industrial (40 c to +85 c) option: extended range (55 c to +125 c) packages: pdil 40, plcc 44 and vqfp 44 options: known good dice and ceramic packages
tsc80251g1d 3 rev. c october 14, 1998 4. block diagram vdd vss vss1 clock unit clock system prescaler await# ea# timers 0, 1 and 2 p3(a16) p2(a158) p1(a17) vss2 p0(ad70) psen# ram 1 kbyte bus interface unit cpu 16bit memory code 16bit memory address ale xtal1 xtal2 rst uart event and waveform controller 16-bit inst. bus 24-bit prog. counter bus 8-bit data bus 24-bit data address bus peripheral interface unit 8-bit internal bus watchdog timer power monitoring i 2 c/spi/ wire controller nmi rom 16 kbytes ports 03 keyboard interface interrupt handler unit figure 1. tsc80251g1d block diagram
tsc80251g1d 4 rev. c october 14, 1998 5. pin description 5.1. pinout p1.5/cex2/miso p3.5/t1 tsc80251g1d p1.7/a17/cex4/sda/mosi/wclk p1.6/cex3/scl/sck/wait# p3.4/t0 p3.3/int1# p3.2/int0# p3.1/txd rst p3.0/rxd p0.4/ad4 p0.5/ad5 p0.6/ad6 p2.7/a15 p2.6/a14 p2.5/a13 p1.4/cex1/ss# p1.3/cex0 p1.2/eci p1.1/t2ex p1.0/t2 p3.6/wr# p3.7/a16/rd# xtal2 xtal1 vss p0.7/ad7 ea# ale psen# p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 figure 2. tsc80251g1d 40pin dip package p1.5/cex2/miso await# p3.5/t1 tsc80251g1d p1.7/a17/cex4/sda/mosi/wclk p1.6/cex3/scl/sck/wait# p3.4/t0 p3.3/int1# p3.2/int0# p3.1/txd rst p3.0/rxd p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea# psen# p2.7/a15 p2.6/a14 p2.5/a13 nmi ale p1.4/cex1/ss# p1.3/cex0 p1.2/eci p1.1/t2ex p1.0/t2 vss1 vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p3.7/a16/rd# xtal2 xtal1 vss vss2 p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p3.6/wr# 7 8 9 10 11 12 13 14 15 16 17 40 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 41 42 43 44 1 2 3 4 5 6 figure 3. tsc80251g1d 44pin plcc package
tsc80251g1d 5 rev. c october 14, 1998 p1.5/cex2/miso await# p3.5/t1 tsc80251g1d p1.7/a17/cex4/sda/mosi/wclk p1.6/cex3/scl/sck/wait# p3.4/t0 p3.3/int1# p3.2/int0# p3.1/txd rst p3.0/rxd p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea# psen# p2.7/a15 p2.6/a14 p2.5/a13 nmi ale p1.4/cex1/ss# p1.3/cex0 p1.2/eci p1.1/t2ex p1.0/t2 vss1 vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p3.7/a16/rd# xtal2 xtal1 vss vss2 p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p3.6/wr# 1 2 3 4 5 6 7 8 9 10 11 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 35 36 37 38 39 40 41 42 43 44 figure 4. tsc80251g1d 44pin vqfp package table 1. tsc80251g1d pin assignment dip plcc vqfp name dip plcc vqfp name 1 39 vss1 23 17 vss2 1 2 40 p1.0/t2 21 24 18 p2.0/a8 2 3 41 p1.1/t2ex 22 25 19 p2.1/a9 3 4 42 p1.2/eci 23 26 20 p2.2/a10 4 5 43 p1.3/cex0 24 27 21 p2.3/a11 5 6 44 p1.4/cex1/ss# 25 28 22 p2.4/a12 6 7 1 p1.5/cex2/miso 26 29 23 p2.5/a13 7 8 2 p1.6/cex3/scl/sck/wait# 27 30 24 p2.6/a14 8 9 3 p1.7/a17/cex4/sda/mosi/wclk 28 31 25 p2.7/a15 9 10 4 rst 29 32 26 psen# 10 11 5 p3.0/rxd 30 33 27 ale 12 6 await# 34 28 nmi 11 13 7 p3.1/txd 31 35 29 ea# 12 14 8 p3.2/int0# 32 36 30 p0.7/ad7 13 15 9 p3.3/int1# 33 37 31 p0.6/ad6 14 16 10 p3.4/t0 34 38 32 p0.5/ad5 15 17 11 p3.5/t1 35 39 33 p0.4/ad4 16 18 12 p3.6/wr# 36 40 34 p0.3/ad3 17 19 13 p3.7/a16/rd# 37 41 35 p0.2/ad2 18 20 14 xtal2 38 42 36 p0.1/ad1 19 21 15 xtal1 39 43 37 p0.0/ad0 20 22 16 vss 40 44 38 vdd
tsc80251g1d 6 rev. c october 14, 1998 5.2. signals table 2. tsc80251g1d signal descriptions signal name type description alternate function a17 o 18 th address bit output to memory as 18th external address bit (a17) in extended bus applications, depending on the values of bits rd0 and rd1 in uconfig0 byte (see no tag). p1.7 a16 o 17 th address bit output to memory as 17th external address bit (a16) in extended bus applications, depending on the values of bits rd0 and rd1 in uconfig0 byte (see no tag). p3.7 a15:8 (1) o address lines upper address lines for the external bus. p2.7:0 ad7:0 (1) i/o address/data lines multiplexed lower address lines and data for the external memory. p0.7:0 ale o address latch enable ale signals the start of an external bus cycle and indicates that valid address information are available onlines a16/a17 and a7:0. an external latch can use ale to demultiplex the address from address/databus. await# i realtime asynchronous wait states input when this pin is active (low level), the memory cycle is stretched until it becomes high. when using the tsc80251g1d as a pinforpin replacement for a 8xc51 product, await# can be unconnected without loss of compatibility or power consumption increase (onchip pullup). not available on dip package. cex4:0 o pca input/output pins cexx are input signals for the pca capture mode and output signals for the pca compare and pwm modes. p1.7:3 ea# i external access enable ea# directs program memory accesses to onchip or offchip code memory. for ea#= 0, all program memory accesses are off-chip. for ea#= 1, an access is on-chip rom if the address is within the range of the onchip rom; otherwise the access is off-chip. the value of ea# is latched at reset. for devices without rom on-chip, ea# must be strapped to ground. eci o pca external clock input eci is the external clock input to the 16bit pca timer. p1.2 miso i/o spi master input slave output line when spi is in master mode, miso receives data from the slave peripheral. when spi is in slave mode, miso outputs data to the master controller. p1.5 mosi i/o spi master output slave input line when spi is in master mode, mosi outputs data to the slave peripheral. when spi is in slave mode, mosi receives data from the master controller. p1.7 int1:0# i external interrupts 0 and 1. int1#/int0# inputs set ie1:0 in the tcon register. if bits it1:0 in the tcon register are set, bits ie1:0 are set by a falling edge on int1#/int0#. if bits it1:0 are cleared, bits ie1:0 are set by a low level on int1#/int0# p3.3:2 nmi i non maskable interrupt holding this pin high for 24 oscillator periods triggers an interrupt. when using the tsc80251g1d as a pinforpin replacement for a 8xc51 product, nmi can be unconnected without loss of compatibility or power consumption increase (onchip pull down). not available on dip package. p0.0:7 i/o port 0 p0 is an 8bit opendrain bidirectional i/o port. ad7:0
tsc80251g1d 7 rev. c october 14, 1998 alternate function description type signal name p1.0:7 i/o port 1 p1 is an 8bit bidirectional i/o port with internal pullups. p1 provides interrupt capability for a keyboard interface. p2.0:7 i/o port 2 p2 is an 8bit bidirectional i/o port with internal pullups. a15:8 p3.0:7 i/o port 3 p3 is an 8bit bidirectional i/o port with internal pullups. psen# o program store enable/read signal output psen# is asserted for a memory address range that depends on bits rd0 and rd1 in ucon- fig0 byte (see no tag). rd# o read or 17 th address bit (a16) read signal output to external data memory depending on the values of bits rd0 and rd1 in uconfig0 byte (see no tag). p3.7 rst i reset input to the chip holding this pin high for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage greater than v ih1 is applied, whether or not the oscillator is running. this pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and vdd. asserting rst when the chip is in idle mode or powerdown mode returns the chip to normal operation. rxd i/o receive serial data rxd sends and receives data in serial i/o mode 0 and receives data in serial modes i/o 1, 2 and 3. p3.0 scl i/o i 2 c serial clock when i 2 c controller is in master mode, scl outputs the serial clock to slave peripherals. when i 2 c controller is in slave mode, scl receives clock from the master controller. p1.6 sck i/o spi serial clock when spi is in master mode, sck outputs clock to the slave peripheral. when spi is in slave mode, sck receives clock from the master controller. p1.6 sda i/o i 2 c serial data sda is the bidirectional i 2 c data line. p1.7 ss# i spi slave select input when in slave mode, ss# enables the slave mode. p1.4 t1:0 i/o timer 1:0 external clock inputs when timer 1:0 operates as a counter, a falling edge on the t1:0 pin increments the count. t2 i/o timer 2 clock input/output for the timer 2 capture mode, t2 is the external clock input. for the timer 2 clockout mode, t2 is the clock output. p1.0 t2ex i timer 2 external input in timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. in autoreload mode, a falling edge causes the timer 2 register to be reloaded. in the updown counter mode, this signal determines the count direction: 1= up, 0= down. p1.1 txd i/o transmit serial data txd outputs the shift clock in serial i/o mode 0 and transmits data in serial i/o modes 1, 2 and 3. p3.1 vdd pwr digital supply voltage connect this pin to +5v or +3v supply voltage. vss gnd circuit ground connect this pin to ground.
tsc80251g1d 8 rev. c october 14, 1998 alternate function description type signal name vss1 gnd secondary ground 1 this ground is provided to reduce ground bounce and improve power supply bypassing. con- nection of this pin to ground is recommended. however, when using the tsc80251g1d as a pinforpin replacement for a 8xc51 product, vss1 can be unconnected without loss of com- patibility. not available on dip package. vss2 gnd secondary ground 2 this ground is provided to reduce ground bounce and improve power supply bypassing. con- nection of this pin to ground is recommended. however, when using the tsc80251g1d as a pinforpin replacement for a 8xc51 product, vss2 can be unconnected without loss of com- patibility. not available on dip package. wait# i realtime synchronous wait states input the realtime wait# input is enabled by setting rtwe bit in wcon (s:a7h). during bus cycles, the external memory system can signal `system ready' to the microcontroller in real time by controlling the wait# input signal. p1.6 wclk o wait clock output the realtime wclk output is enabled by setting rtwce bit in wcon (s:a7h). when en- abled, the wclk output produces a square wave signal with a period of one half the oscillator frequency. p1.7 wr# o write write signal output to external memory. p3.6 xtal1 i input to the onchip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. xtal1 is the clock source for internal tim- ing. xtal2 o output of the onchip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, leave xtal2 unconnected. note: 1. the description of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the nonpage mode chip configuration. if the chip is configured in p age mode operation, port 0 carries the lower address bits (a7:0) while port 2 carries the upper address bits (a15:8) and the data (d7:0) .
tsc80251g1d 9 rev. c october 14, 1998 6. address spaces the tsc80251g1d implements four different address spaces: onchip rom program/code memory (not present in romless devices) onchip ram data memory special function registers (sfrs) configuration array 6.1. program/code memory the tsc83251g1d implements 16 kbytes of onchip program/code memory. figure 5 shows the split of the internal and external program/code memory spaces. if ea# is tied to a high level, the 16kbyte onchip program memory is mapped in the lower part of segment ff: where the c251 core jumps after reset. the rest of the program/code memory space is mapped to the external memory. if ea# is tied to a low level, the internal program/code memory is not used and all the accesses are directed to the external memory. for the masked rom products, the internal program/code is provided in a masked rom. for the romless products, there is no possible internal program/code and ea# must be tied to a low level. ff:3fffh ff:0000h fd:ffffh 02:0000h reserved onchip memory rom code program/code segments program/code external memory space ff:ffffh ff:4000h fe:0000h 01:ffffh 01:0000h 00:0000h 00:ffffh fe:ffffh ea#= 1 16 kbytes 48 kbytes 16 kbytes 64 kbytes 128 kbytes ea#= 0 figure 5. program/code memory mapping notes: special care should be taken when the program counter (pc) increments: if the program executes exclusively from onchip code memory (not from external memory), beware of executing code from the upp er eight bytes of the onchip rom (ff:3ff8hff:3ffffh). because of its pipeline capability, the tsc80251g1d may attempt to prefetch code from ext ernal memory (at an address above ff:3ffffh) and thereby disrupt i/o ports 0 and 2. fetching code constants from these 8 bytes does n ot affect ports 0 and 2. when pc reaches the end of segment ff:, it loops to the reset address ff:0000h (for compatibility with the c51 architecture). when pc increments beyond the end of segment fe:, it continues at the reset address ff:0000h (linearity). when pc increments beyond the end of seg ment 01:, it loops to the beginning of segment 00: (this prevents from its going into the reserved area).
tsc80251g1d 10 rev. c october 14, 1998 6.2. data memory the tsc80251g1d implements 1 kbyte of onchip data ram. figure 6 shows the split of the internal and external data memory spaces. this memory is mapped in the data space just over the 32 bytes of registers area (see tsc80251 programmers' guide). hence, the part of the onchip ram located from 20h to ffh is bit addressable. this onchip ram is not accessible through the program/code memory space. for faster computation with the onchip rom code of the tsc83251g1d, its upper 8 kbytes are also mapped in the upper part of the region 00: if the onchip code memory map configuration bit is cleared (emap# bit in uconfig1 byte, see figure 8). however, if ea# is tied to a low level, the tsc80251g1d derivative is running as a romless product and the code is actually fetched in the corresponding external memory (i.e. the upper 8 kbytes of the lower 16 kbytes of the segment ff:). if emap# bit is set, the onchip rom is not accessible through the region 00:. all the accesses to the portion of the data space with no onchip memory mapped onto are redirected to the external memory. ff:3fffh ff:0000h 01:0000h 00:ffffh 00:e000h data external memory space onchip memory rom code ff:ffffh ff:4000h 00:0420h fe:ffffh 8 kbytes 8 kbytes 1 kbyte 32 bytes reg. emap#= 1 data segments 48 kbytes 16 kbytes 8 kbytes 56 kbytes ram data fe:0000h 01:ffffh 64 kbytes 64 kbytes emap#= 0 ea#= 1 00:dfffh fd:ffffh 02:0000h reserved ea#= 0 figure 6. data memory mapping 6.3. special function registers the special function registers (sfrs) of the tsc80251g1d derivatives fall into the categories detailed in table 3 to table 11. sfrs are placed in a reserved onchip memory region s: which is not represented in the data memory mapping (figure 6). the relative addresses within s: of these sfrs are provided together with their reset values in table 12. they are upward compatible with the sfrs of the standard 80c51 and the intel's 80c251sx family. in this table, the c251 core registers are in italics and are described in the tsc80251 programmer's guide. the other sfrs are described in the tsc80251g1d design guide. all the sfrs are bitaddressable using the c251 instruction set.
tsc80251g1d 11 rev. c october 14, 1998 table 3. c251 core sfrs mnemonic name mnemonic name acc (1) accumulator sph (1) stack pointer high msb of spx b (1) b register dpl (1) data pointer low byte lsb of dptr psw program status word dph (1) data pointer high byte msb of dptr psw1 program status word 1 dpxl (1) data pointer extended low byte of dpx region number sp (1) stack pointer lsb of spx note: 1. these sfrs can also be accessed by their corresponding registers in the register file. table 4. i/o port sfrs mnemonic name mnemonic name p 0 port 0 p 2 port 2 p 1 port 1 p 3 port 3 table 5. timers sfrs mnemonic name mnemonic name tl0 timer/counter 0 low byte tmod timer/counter 0 and 1 modes th0 timer/counter 0 high byte t2con timer/counter 2 control tl1 timer/counter 1 low byte t2mod timer/counter 2 mode th1 timer/counter 1 high byte rcap2l timer/counter 2 reload/capture low byte tl2 timer/counter 2 low byte rcap2h timer/counter 2 reload/capture high byte th2 timer/counter 2 high byte wdtrst watchdog timer reset tcon timer/counter 0 and 1 control table 6. serial i/o port sfrs mnemonic name mnemonic name scon serial control saddr slave address sbuf serial data buffer brl baud rate reload saden slave address mask bdrcon baud rate control table 7. sslc sfrs mnemonic name mnemonic name sscon synchronous serial control ssadr synchronous serial address ssdat synchronous serial data ssbr synchronous serial bit rate sscs synchronous serial control and status
tsc80251g1d 12 rev. c october 14, 1998 table 8. event waveform control sfrs mnemonic name mnemonic name ccon ewcpca timer/counter control ccap1l ewcpca compare capture module 1 low register cmod ewcpca timer/counter mode ccap2l ewcpca compare capture module 2 low register cl ewcpca timer/counter low register ccap3l ewcpca compare capture module 3 low register ch ewcpca timer/counter high register ccap4l ewcpca compare capture module 4 low register ccapm0 ewcpca timer/counter mode 0 ccap0h ewcpca compare capture module 0 high register ccapm1 ewcpca timer/counter mode 1 ccap1h ewcpca compare capture module 1 high register ccapm2 ewcpca timer/counter mode 2 ccap2h ewcpca compare capture module 2 high register ccapm3 ewcpca timer/counter mode 3 ccap3h ewcpca compare capture module 3 high register ccapm4 ewcpca timer/counter mode 4 ccap4h ewcpca compare capture module 4 high register ccap0l ewcpca compare capture module 0 low register table 9. system management sfrs mnemonic name mnemonic name pcon power control ckrl clock reload powm power management wcon synchronous realtime wait state control pfilt power filter table 10. interrupt sfrs mnemonic name mnemonic name ie0 interrupt enable control 0 ipl0 interrupt priority control low 0 ie1 interrupt priority control 1 iph1 interrupt priority control high 1 iph0 interrupt priority control high 0 ipl1 interrupt priority control low 1 table 11. keyboard interface sfrs mnemonic name mnemonic name p1ie port 1 input interrupt enable p1ls port 1 level selection p1f port 1 flag
tsc80251g1d 13 rev. c october 14, 1998 table 12. sfr addresses and reset values 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ch 0000 0000 ccap0h 0000 0000 ccap1h 0000 0000 ccap2h 0000 0000 ccap3h 0000 0000 ccap4h 0000 0000 ffh f0h b (1) 0000 0000 f7h e8h cl 0000 0000 ccap0l 0000 0000 ccap1l 0000 0000 ccap2l 0000 0000 ccap3l 0000 0000 ccap4l 0000 0000 efh e0h acc (1) 0000 0000 e7h d8h ccon 00x0 0000 cmod 00xx x000 ccapm0 x000 0000 ccapm1 x000 0000 ccapm2 x000 0000 ccapm3 x000 0000 ccapm4 x000 0000 dfh d0h psw (1) 0000 0000 psw1 (1) 0000 0000 d7h c8h t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 cfh c0h c7h b8h ipl0 x000 0000 saden 0000 0000 sph (1) 0000 0000 bfh b0h p3 1111 1111 ie1 xx0x xxx0 ipl1 xx0x xxx0 iph1 xx0x xxx0 iph0 x000 0000 b7h a8h ie0 0000 0000 saddr 0000 0000 afh a0h p2 1111 1111 wdtrst 1111 1111 wcon xxxx xx00 a7h 98h scon 0000 0000 sbuf xxxx xxxx brl 0000 0000 bdrcon xxx0 0000 p1ls 0000 0000 p1ie 0000 0000 p1f 0000 0000 9fh 90h p1 1111 1111 ssbr 0000 0000 sscon (2) sscs (3) ssdat 0000 0000 ssadr 0000 0000 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 ckrl 0000 1000 powm 0xxx 0xxx 8fh 80h p0 1111 1111 sp 0000 0111 dpl (1) 0000 0000 dph (1) 0000 0000 dpxl (1) 0000 0001 pfilt xxxx xxxx pcon 0000 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f reserved notes: 1. these registers are described in the tsc80251 programmer's guide (c251 core registers). 2. in i 2 c and spi modes, sscon is splitted in two separate registers. sscon reset value is 0000 0000 in i 2 c mode and 0000 0100 in spi mode. 3. in read and write modes, sscs is splitted in two separate registers. sscs reset value is 1111 1000 in read mode and 0000 0000 in write mode.
tsc80251g1d 14 rev. c october 14, 1998 6.4. configuration bytes the tsc80251g1d derivatives provide user design flexibility by configuring certain operating features at device reset. these features fall into the following categories: external memory interface (page mode, address bits, programmed wait states and the address range for rd#, wr#, and psen#) source mode/binary mode opcodes selection of bytes stored on the stack by an interrupt mapping of the upper portion of onchip code memory to region 00: two user configuration bytes uconfig0 (see figure 7) and uconfig1 (see figure 8) provide the information. when ea# is tied to a low level, the configuration bytes are fetched from the external address space. the tsc80251g1d derivatives reserve the top eight bytes of the memory address space (ff:fff8h-ff:ffffh) for an external 8byte configuration array. only two bytes are actually used: uconfig0 at ff:fff8h and uconfig1 at ff:fff9h. for the mask rom devices, configuration information is stored in onchip memory (see rom verifying). when ea# is tied to a high level, the configuration information is retrieved from the onchip memory instead of the external address space and there is no restriction in the usage of the external memory. uconfig0 configuration byte 0 76543210 wsa1# wsa0# xale# rd1 rd0 page# src bit number bit mnemonic description 7 reserved set this bit when writing to uconfig0. 6 wsa1# wait state a bits select the number of wait states for rd#, wr# and psen# signals for external memory accesses (all re- gions except 01:). ws a1# ws a 0 # nu m be r o f wa i t states 5 wsa0# wsa1# wsa0# number of wait states 003 012 101 110 4 xale# extend ale bit clear to extend the duration of the ale pulse from t osc to 3 t osc. set to minimize the duration of the ale pulse to 1 t osc . 3 rd1 memory signal select bits specify a 18 bit 17 bit or 16 bit external address bus and the usage of rd# wr# and psen# signals 2 rd0 specify a 18bit, 17bit or 16bit external address bus and the usage of rd#, wr# and psen# signals (see table 13). 1 page# page mode select bit (1) clear to select the faster page mode with a15:8/d7:0 on port 2 and a7:0 on port 0. set to select the nonpage mode (2) with a15:8 on port 2 and a7:0/d7:0 on port 0. 0 src source mode/binary mode select bit clear to select the binary mode. set to select the source mode. notes: 1. uconfig0 is fetched twice so it can be properly read both in page or nonpage modes. if p2.1 is cleared during the first data phase, a page mode configuration is used, otherwise the subsequent fetches are performed in nonpage mode. 2. this selection provides compatibility with the standard 80c51 hardware which is multiplexing the address lsb and the data on port 0. figure 7. configuration byte 0
tsc80251g1d 15 rev. c october 14, 1998 uconfig1 configuration byte 1 76543210 intr wsb wsb1# wsb0# emap# bit number bit mnemonic description 7 reserved set this bit when writing to uconfig1. 6 reserved set this bit when writing to uconfig1. 5 reserved set this bit when writing to uconfig1. 4 intr interrupt mode bit (1) clear so that the interrupts push two bytes onto the stack (the two lower bytes of the pc register). set so that the interrupts push four bytes onto the stack (the three bytes of the pc register and the psw1 register). 3 wsb wait state b bit (2) clear to generate one wait state for memory region 01:. set for no wait states for memory region 01:. 2 wsb1# wait state b bits select the number of wait states for rd#, wr# and psen# signals for external memory accesses (only region 01:). ws b1# ws b 0 # nu m be r o f wa i t states 1 wsb0# wsb1# wsb0# number of wait states 003 012 101 110 0 emap# onchip code memory map bit clear to map the upper 8 kbytes of onchip code memory (at ff:2000hff:3fffh) to the data space (at 00:e000h00:ffffh). set not to map the upper 8 kbytes of onchip code memory (at ff:2000hff:3fffh) to the data space. notes: 1. two or four bytes are transparently popped according to intr when using the reti instruction. intr must be set if interrupts are used with code executing outside region ff:. 2. use only for step a compatibility; set this bit when wsb1:0# are used. figure 8. configuration byte 1 table 13. address ranges and usage of rd#, wr# and psen# signals rd1 rd0 p1.7 p3.7/rd# psen# wr# external memory 0 0 a17 a16 read signal for all external memory locations write signal for all external memory locations 256 kbytes 0 1 i/o pin a16 read signal for all external memory locations write signal for all external memory locations 128 kbytes 1 0 i/o pin i/o pin read signal for all external memory locations write signal for all external memory locations 64 kbytes 1 1 i/o pin read signal for regions 00: and 01: read signal for regions fe: and ff: write signal for all external memory locations 2 64 kbytes (1) note: 1. this selection provides compatibility with the standard 80c51 hardware which has separate external memory spaces for data and code.
tsc80251g1d 16 rev. c october 14, 1998 7. instruction set summary this section contains tables that summarize the instruction set. for each instruction there is a short description, its length in bytes, and its execution time in states (one state time is equal to two system clock cycles). there are two concurrent processes limiting the effective instruction throughput: instruction fetch instruction execution table 20 to table 34 assume code executing from onchip memory, then the cpu is fetching 16bit at a time and this is never limiting the execution speed. if the code is fetched from external memory, a prefetch queue will store instructions ahead of execution to optimize the memory bandwidth usage when slower instructions are executed. however, the effective speed may be limited depending on the average size of instructions (for the considered section of the program flow). the maximum average instruction throughput is provided by table 14 depending on the external memory configuration (from page mode to nonpage mode and the maximum number of wait states). if the average size of instructions is not an integer, the maximum effective throughput is found by pondering the number of states for the neighbor integer values. table 14. minimum number of states per instruction for given average sizes average size of instruct i ons page mode nonpage mode (states) instructions (bytes) page mode (states) 0 wait state 1 wait state 2 wait states 3 wait states 4 wait states 1 1 2 3 4 5 6 2 2 4 6 8 10 12 3 3 6 9 12 15 18 4 4 8 12 16 20 24 5 5 10 15 20 25 30 if the average execution time of the considered instructions is larger than the number of states given by table 14, this larger value will prevail as the limiting factor. otherwise, the value from table 14 must be taken. this is providing a fair estimation of the execution speed but only the actual code execution can provide the final value. 7.1. notation for instruction operands table 15 to table 19 provide notation for instruction operands. table 15. notation for direct addressing direct address description c251 c51 dir8 a direct 8-bit address. this can be a memory address (00h-7fh) or a sfr address (80h-ffh). it is a byte (default), word or double word depending on the other operand. dir16 a 16-bit memory address (00:0000h-00:ffffh) used in direct addressing. table 16. notation for immediate addressing immediate address description c251 c51 #data an 8-bit constant that is immediately addressed in an instruction #data16 a 16-bit constant that is immediately addressed in an instruction #0data16 #1data16 a 32-bit constant that is immediately addressed in an instruction. the upper word is filled with zeros (#0data16) or ones (#1data16). #short a constant, equal to 1, 2, or 4, that is immediately addressed in an instruction.
tsc80251g1d 17 rev. c october 14, 1998 table 17. notation for bit addressing direct address description c251 c51 bit51 a directly addressed bit (bit number= 00h-ffh) in memory or an sfr. bits 00h-7fh are the 128 bits in byte locations 20h-2fh in the on-chip ram. bits 80h-ffh are the 128 bits in the 16 sfrs with addresses that end in 0h or 8h, s:80h, s:88h, s:90h,..., s:f0h, s:f8h. bit a directly addressed bit in memory locations 00:0020h-00:007fh or in any defined sfr. table 18. notation for destination in control instructions direct address description c251 c51 rel a signed (two's complement) 8-bit relative address. the destination is 128 to +127 bytes relative to the next instruction's first byte. addr11 an 11-bit target address. the target is in the same 2-kbyte block of memory as the next instruction's first byte. addr16 a 16-bit target address. the target can be anywhere within the same 64-kbyte region as the next instruction's first byte. addr24 a 24-bit target address. the target can be anywhere within the 16mbyte address space. table 19. notation for register operands register description c251 c51 @ri a memory location (00h-ffh) addressed indirectly via byte registers r0 or r1 rn n byte register r0-r7 of the currently selected register bank byte register index: n= 0-7 rm rmd rms m, md, ms byte register r0-r15 of the currently selected register file destination register source register byte register index: m, md, ms= 0-15 wrj wrjd wrjs @wrj @wrj +dis16 j, jd, js word register wr0, wr2, ..., wr30 of the currently selected register file destination register source register a memory location (00:0000h-00:ffffh) addressed indirectly through word register wr0-wr30, is the target address for jump instructions. a memory location (00:0000h-00:ffffh) addressed indirectly through word register (wr0-wr30) + 16bit signed (two's complement) displacement value word register index: j, jd, js= 0-30 drk drkd drks @drk @drk +dis16 k, kd, ks dword register dr0, dr4, ..., dr28, dr56, dr60 of the currently selected register file destination register source register a memory location (00:0000h-ff:ffffh) addressed indirectly through dword register dr0-dr28, dr56 and dr60, is the target address for jump instruction a memory location (00:0000h-ff:ffffh) addressed indirectly through dword register (dr0-dr28, dr56, dr60) + 16bit (two's complement) signed displacement value dword register index: k, kd, ks= 0, 4, 8..., 28, 56, 60
tsc80251g1d 18 rev. c october 14, 1998 7.2. size and execution time for instruction families table 20. summary of add and subtract instructions add add , dest opnd dest opnd + src opnd subtract sub , dest opnd dest opnd src opnd add with carry addc , (a) (a) + src opnd + (cy) subtract with borrow subb , (a) (a) src opnd (cy) mnemon i c (1) comments binary mode source mode mnemonic , (1) comments bytes states bytes states a, rn register to acc 1 1 2 2 add a, dir8 direct address to acc 2 1 (2) 2 1 (2) add a, @ri indirect address to acc 1 2 2 3 a, #data immediate data to acc 2 1 2 1 rmd, rms byte register to/from byte register 3 2 2 1 wrjd, wrjs word register to/from word register 3 3 2 2 drkd, drks dword register to/from dword register 3 5 2 4 rm, #data immediate 8-bit data to/from byte register 4 3 3 2 wrj, #data16 immediate 16-bit data to/from word register 5 4 4 3 drk, #0data16 16-bit unsigned immediate data to/from dword register 5 6 4 5 add / sub rm, dir8 direct address (onchip ram or sfr) to/from byte register 4 3 (2) 3 2 (2) wrj, dir8 direct address (onchip ram or sfr) to/from word register 4 4 3 3 rm, dir16 direct address (64k) to/from byte register 5 3 (3) 4 2 (3) wrj, dir16 direct address (64k) to/from word register 5 4 (4) 4 3 (4) rm, @wrj indirect address (64k) to/from byte register 4 3 (3) 3 2 (3) rm, @drk indirect address (16m) to/from byte register 4 4 (3) 3 3 (3) a, rn register to/from acc with carry 1 1 2 2 addc / subb a, dir8 direct address (onchip ram or sfr) to/from acc with carry 2 1 (2) 2 1 (2) subb a, @ri indirect address to/from acc with carry 1 2 2 3 a, #data immediate data to/from acc with carry 2 1 2 1 notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr . 3. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). 4. if this instruction addresses external memory location, add 2(n+2) to the number of states (n: number of wait states).
tsc80251g1d 19 rev. c october 14, 1998 table 21. summary of increment and decrement instructions increment inc dest opnd dest opnd + 1 increment inc , dest opnd dest opnd + src opnd decrement dec dest opnd dest opnd 1 decrement dec , dest opnd dest opnd src opnd mnemon i c (1) comments binary mode source mode mnemonic , (1) comments bytes states bytes states a acc by 1 1 1 1 1 inc rn register by 1 1 1 2 2 inc dec dir8 direct address (onchip ram or sfr) by 1 2 2 (2) 2 2 (2) @ri indirect address by 1 1 3 2 4 inc rm, #short byte register by 1, 2, or 4 3 2 2 1 inc dec wrj, #short word register by 1, 2, or 4 3 2 2 1 inc drk, #short double word register by 1, 2, or 4 3 4 2 3 dec drk, #short double word register by 1, 2, or 4 3 5 2 4 inc dptr data pointer by 1 1 1 1 1 notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. if this instruction addresses an i/o port (px, x= 0-3), add 2 to the number of states. add 3 if it addresses a peripheral sfr . table 22. summary of compare instructions compare cmp , dest opnd src opnd mnemon i c (1) comments binary mode source mode mnemonic , (1) comments bytes states bytes states rmd, rms register with register 3 2 2 1 wrjd, wrjs word register with word register 3 3 2 2 drkd, drks dword register with dword register 3 5 2 4 rm, #data register with immediate data 4 3 3 2 wrj, #data16 word register with immediate 16-bit data 5 4 4 3 drk, #0data16 dword register with zero-extended 16-bit immediate data 5 6 4 5 cmp drk, #1data16 dword register with one-extended 16-bit immediate data 5 6 4 5 rm, dir8 direct address (onchip ram or sfr) with byte register 4 3 (1) 3 2 (1) wrj, dir8 direct address (onchip ram or sfr) with word register 4 4 3 3 rm, dir16 direct address (64k) with byte register 5 3 (2) 4 2 (2) wrj, dir16 direct address (64k) with word register 5 4 (3) 4 3 (3) rm, @wrj indirect address (64k) with byte register 4 3 (2) 3 2 (2) rm, @drk indirect address (16m) with byte register 4 4 (2) 3 3 (2) notes: 1. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr . 2. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). 3. if this instruction addresses external memory location, add 2(n+2) to the number of states (n: number of wait states).
tsc80251g1d 20 rev. c october 14, 1998 table 23. summary of logical instructions (1/2) logical and (1) anl , dest opnd dest opnd l src opnd logical or (1) orl , dest opnd dest opnd v src opnd logical exclusive or (1) xrl , dest opnd dest opnd " src opnd clear (1) clr a (a) 0 complement (1) cpl a (a) ? (a) rotate left rl a (a) n+1 (a) n , n= 0..6 (a) 0 (a) 7 rotate left carry rlc a (a) n+1 (a) n , n= 0..6 (cy) (a) 7 (a) 0 (cy) rotate right rr a (a) n1 (a) n , n= 7..1 (a) 7 (a) 0 rotate right carry rrc a (a) n1 (a) n , n= 7..1 (cy) (a) 0 (a) 7 (cy) mnemon i c (2) comments binary mode source mode mnemonic , (2) comments bytes states bytes states a, rn register to acc 1 1 2 2 a, dir8 direct address (onchip ram or sfr) to acc 2 1 (3) 2 1 (3) a, @ri indirect address to acc 1 2 2 3 a, #data immediate data to acc 2 1 2 1 dir8, a acc to direct address 2 2 (4) 2 2 (4) dir8, #data immediate 8bit data to direct address 3 3 (4) 3 3 (4) rmd, rms byte register to byte register 3 2 2 1 anl orl wrjd, wrjs word register to word register 3 3 2 2 orl xrl rm, #data immediate 8-bit data to byte register 4 3 3 2 wrj, #data16 immediate 16-bit data to word register 5 4 4 3 rm, dir8 direct address to byte register 4 3 (3) 3 2 (3) wrj, dir8 direct address to word register 4 4 3 3 rm, dir16 direct address (64k) to byte register 5 3 (5) 4 2 (5) wrj, dir16 direct address (64k) to word register 5 4 (6) 4 3 (6) rm, @wrj indirect address (64k) to byte register 4 3 (5) 3 2 (5) rm, @drk indirect address (16m) to byte register 4 4 (5) 3 3 (5) clr a clear acc 1 1 1 1 cpl a complement acc 1 1 1 1 rl a rotate acc left 1 1 1 1 rlc a rotate acc left through cy 1 1 1 1 rr a rotate acc right 1 1 1 1 rrc a rotate acc right through cy 1 1 1 1 notes: 1. logical instructions that affect a bit are in table 29. 2. a shaded cell denotes an instruction in the c51 architecture. 3. if this instruction addresses an i/o port (px, x= 03), add 1 to the number of states. add 2 if it addresses a peripheral sfr . 4. if this instruction addresses an i/o port (px, x= 03), add 2 to the number of states. add 3 if it addresses a peripheral sfr . 5. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). 6. if this instruction addresses external memory location, add 2(n+2) to the number of states (n: number of wait states).
tsc80251g1d 21 rev. c october 14, 1998 table 24. summary of logical instructions (2/2) shift left logical sll 0 0 n+1 n , n= 0..msb1 (cy) msb shift right arithmetic sra msb msb n1 n , n= msb..1 (cy) 0 shift right logical srl msb 0 n1 n , n= msb..1 (cy) 0 swap swap a a 3:0 a 7:4 mnemon i c (1) comments binary mode source mode mnemonic , (1) comments bytes states bytes states sll rm shift byte register left through the msb 3 2 2 1 sll wrj shift word register left through the msb 3 2 2 1 sra rm shift byte register right 3 2 2 1 sra wrj shift word register right 3 2 2 1 srl rm shift byte register left 3 2 2 1 srl wrj shift word register left 3 2 2 1 swap a swap nibbles within acc 1 2 1 2 note: 1. a shaded cell denotes an instruction in the c51 architecture. table 25. summary of multiply, divide and decimal-adjust instructions multiply mul ab (b:a) (a) (b) mul , extended dest opnd dest opnd src opnd divide div ab (a) quotient ((a) M (b)) (b) remainder ((a) M (b)) divide div , ext. dest opnd high quotient (dest opnd M src opnd) ext. dest opnd low remainder (dest opnd M src opnd) decimal-adjust acc da a if [[(a) 3:0 > 9] [(ac)= 1]] for addition (bcd) then (a) 3:0 (a) 3:0 + 6 !affects cy; if [[(a) 7:4 > 9] [(cy)= 1]] then (a) 7:4 (a) 7:4 + 6 mnemon i c (1) comments binary mode source mode mnemonic , (1) comments bytes states bytes states ab multiply a and b 1 5 1 5 mul rmd, rms multiply byte register and byte register 3 6 2 5 wrjd, wrjs multiply word register and word register 3 12 2 11 ab divide a and b 1 10 1 10 div rmd, rms divide byte register and byte register 3 11 2 10 wrjd, wrjs divide word register and word register 3 21 2 20 da a decimal adjust acc 1 1 1 1 note: 1. a shaded cell denotes an instruction in the c51 architecture.
tsc80251g1d 22 rev. c october 14, 1998 table 26. summary of move instructions (1/3) move to high word movh , dest opnd 31:16 src opnd move with sign extension movs , dest opnd src opnd with sign extend move with zero extension movz , dest opnd src opnd with zero extend move code movc a, (a) src opnd move extended movx , dest opnd src opnd mnemon i c (1) comments binary mode source mode mnemonic , (1) comments bytes states bytes states movh drk, #data16 16-bit immediate data into upper word of dword register 5 3 4 2 movs wrj, rm byte register to word register with sign extension 3 2 2 1 movz wrj, rm byte register to word register with zeros extension 3 2 2 1 movc a, @a +dptr code byte relative to dptr to acc 1 6 (3) 1 6 (3) movc a, @a +pc code byte relative to pc to acc 1 6 (3) 1 6 (3) a, @ri extended memory (8-bit address) to acc (2) 1 4 1 5 movx a, @dptr extended memory (16-bit address) to acc (2) 1 3 (4) 1 3 (4) movx @ri, a acc to extended memory (8-bit address) (2) 1 4 1 4 @dptr, a acc to extended memory (16-bit address) (2) 1 4 (3) 1 4 (3) notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. extended memory addressed is in the region specified by dpxl (reset value= 01h). 3. if this instruction addresses external memory location, add n+1 to the number of states (n: number of wait states). 4. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). table 27. summary of move instructions (2/3) move (1) mov , dest opnd src opnd mnemon i c (2) comments binary mode source mode mnemonic , (2) comments bytes states bytes states a, rn register to acc 1 1 2 2 a, dir8 direct address (onchip ram or sfr) to acc 2 1 (3) 2 1 (3) a, @ri indirect address to acc 1 2 2 3 a, #data immediate data to acc 2 1 2 1 rn, a acc to register 1 1 2 2 rn, dir8 direct address (onchip ram or sfr) to register 2 1 (3) 3 2 (3) mov rn, #data immediate data to register 2 1 3 2 dir8, a acc to direct address 2 2 (3) 2 2 (3) dir8, rn register to direct address 2 2 (3) 3 3 (3) dir8, dir8 direct address to direct address 3 3 (4) 3 3 (4) dir8, @ri indirect address to direct address 2 3 (3) 3 4 (3) dir8, #data immediate data to direct address 3 3 (3) 3 3 (3) @ri, a acc to indirect address 1 3 2 4 @ri, dir8 direct address to indirect address 2 3 (3) 3 4 (3) @ri, #data immediate data to indirect address 2 3 3 4 dptr, #data16 load data pointer with a 16-bit constant 3 2 3 2 notes: 1. instructions that move bits are in table 29. 2. move instructions from the c51 architecture. 3. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr . 4. apply note 3 for each dir8 operand.
tsc80251g1d 23 rev. c october 14, 1998 table 28. summary of move instructions (3/3) move (1) mov , dest opnd src opnd mnemon i c (2) comments binary mode source mode mnemonic , (2) comments bytes states bytes states rmd, rms byte register to byte register 3 2 2 1 wrjd, wrjs word register to word register 3 2 2 1 drkd, drks dword register to dword register 3 3 2 2 rm, #data immediate 8-bit data to byte register 4 3 3 2 wrj, #data16 immediate 16-bit data to word register 5 3 4 2 drk, #0data16 zero-ext 16bit immediate data to dword register 5 5 4 4 drk, #1data16 one-ext 16bit immediate data to dword register 5 5 4 4 rm, dir8 direct address to byte register 4 3 (3) 3 2 (3) wrj, dir8 direct address to word register 4 4 3 3 drk, dir8 direct address to dword register 4 6 3 5 rm, dir16 direct address (64k) to byte register 5 3 (4) 4 2 (4) wrj, dir16 direct address (64k) to word register 5 4 (5) 4 3 (5) drk, dir16 direct address (64k) to dword register 5 6 (6) 4 5 (6) rm, @wrj indirect address (64k) to byte register 4 3 (4) 3 2 (4) rm, @drk indirect address (16m) to byte register 4 4 (4) 3 3 (4) wrjd, @wrjs indirect address (64k) to word register 4 4 (5) 3 3 (5) wrj, @drk indirect address (16m) to word register 4 5 (5) 3 4 (5) dir8, rm byte register to direct address 4 4 (3) 3 3 (3) mov dir8, wrj word register to direct address 4 5 3 4 dir8, drk dword register to direct address 4 7 3 6 dir16, rm byte register to direct address (64k) 5 4 (4) 4 3 (4) dir16, wrj word register to direct address (64k) 5 5 (5) 4 4 (5) dir16, drk dword register to direct address (64k) 5 7 (6) 4 6 (6) @wrj, rm byte register to indirect address (64k) 4 4 (4) 3 3 (4) @drk, rm byte register to indirect address (16m) 4 5 (4) 3 4 (4) @wrjd, wrjs word register to indirect address (64k) 4 5 (5) 3 4 (5) @drk, wrj word register to indirect address (16m) 4 6 (5) 3 5 (5) rm, @wrj +dis16 indirect with 16bit dis (64k) to byte register 5 6 (4) 4 5 (4) wrj, @wrj +dis16 indirect with 16bit dis (64k) to word register 5 7 (5) 4 6 (5) rm, @drk +dis24 indirect with 16bit dis (16m) to byte register 5 7 (4) 4 6 (4) wrj, @wrj +dis24 indirect with 16bit dis (16m) to word register 5 8 (5) 4 7 (5) @wrj +dis16, rm byte register to indirect with 16bit dis (64k) 5 6 (4) 4 5 (4) @wrj +dis16, wrj word register to indirect with 16bit dis (64k) 5 7 (5) 4 6 (5) @drk +dis24, rm byte register to indirect with 16bit dis (16m) 5 7 (4) 4 6 (4) @drk +dis24, wrj word register to indirect with 16bit dis (16m) 5 8 (5) 4 7 (5) notes: 1. instructions that move bits are in table 29. 2. move instructions unique to the c251 architecture. 3. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr . 4. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). 5. if this instruction addresses external memory location, add 2(n+1) to the number of states (n: number of wait states). 6. if this instruction addresses external memory location, add 4(n+2) to the number of states (n: number of wait states).
tsc80251g1d 24 rev. c october 14, 1998 table 29. summary of bit instructions clear bit clr dest opnd 0 set bit setb dest opnd 1 complement bit cpl dest opnd ? bit and carry with bit anl cy, (cy) (cy) src opnd and carry with complement of bit anl cy, / (cy) (cy) ? src opnd or carry with bit orl cy, (cy) (cy) src opnd or carry with complement of bit orl cy, / (cy) (cy) ? src opnd move bit to carry mov cy, (cy) src opnd move bit from carry mov , cy dest opnd (cy) mnemon i c (1) comments binary mode source mode mnemonic , (1) comments bytes states bytes states cy clear carry 1 1 1 1 clr bit51 clear direct bit 2 2 (3) 2 2 (3) bit clear direct bit 4 4 (3) 3 3 (3) cy set carry 1 1 1 1 setb bit51 set direct bit 2 2 (3) 2 2 (3) bit set direct bit 4 4 (3) 3 3 (3) cy complement carry 1 1 1 1 cpl bit51 complement direct bit 2 2 (3) 2 2 (3) bit complement direct bit 4 4 (3) 3 3 (3) cy, bit51 and direct bit to carry 2 1 (2) 2 1 (2) anl cy, bit and direct bit to carry 4 3 (2) 3 2 (2) anl cy, /bit51 and complemented direct bit to carry 2 1 (2) 2 1 (2) cy, /bit and complemented direct bit to carry 4 3 (2) 3 2 (2) cy, bit51 or direct bit to carry 2 1 (2) 2 1 (2) orl cy, bit or direct bit to carry 4 3 (2) 3 2 (2) orl cy, /bit51 or complemented direct bit to carry 2 1 (2) 2 1 (2) cy, /bit or complemented direct bit to carry 4 3 (2) 3 2 (2) cy, bit51 move direct bit to carry 2 1 (2) 2 1 (2) mov cy, bit move direct bit to carry 4 3 (2) 3 2 (2) mov bit51, cy move carry to direct bit 2 2 (3) 2 2 (3) bit, cy move carry to direct bit 4 4 (3) 3 3 (3) notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. if this instruction addresses an i/o port (px, x= 03), add 1 to the number of states. add 2 if it addresses a peripheral sfr . 3. if this instruction addresses an i/o port (px, x= 03), add 2 to the number of states. add 3 if it addresses a peripheral sfr .
tsc80251g1d 25 rev. c october 14, 1998 table 30. summary of exchange, push and pop instructions exchange bytes xch a, (a) src opnd exchange digit xchd a, (a) 3:0 src opnd 3:0 push push (sp) (sp) +1; ((sp)) src opnd; (sp) (sp) + size (src opnd) 1 pop pop (sp) (sp) size (dest opnd) + 1; dest opnd ((sp)); (sp) (sp) 1 mnemon i c (1) comments binary mode source mode mnemonic , (1) comments bytes states bytes states xch a, rn acc and register 1 3 2 4 xch a, dir8 acc and direct address (onchip ram or sfr) 2 3 (3) 2 3 (3) a, @ri acc and indirect address 1 4 2 5 xchd a, @ri acc low nibble and indirect address (256 bytes) 1 4 2 5 dir8 push direct address onto stack 2 2 (2) 2 2 (2) #data push immediate data onto stack 4 4 3 3 push #data16 push 16-bit immediate data onto stack 5 5 4 5 push rm push byte register onto stack 3 4 2 3 wrj push word register onto stack 3 5 2 4 drk push double word register onto stack 3 9 2 8 dir8 pop direct address (onchip ram or sfr) from stack 2 3 (2) 2 3 (2) pop rm pop byte register from stack 3 3 2 2 pop wrj pop word register from stack 3 5 2 4 drk pop double word register from stack 3 9 2 8 notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr . 3. if this instruction addresses an i/o port (px, x= 0-3), add 2 to the number of states. add 3 if it addresses a peripheral sfr . table 31. summary of conditional jump instructions (1/2) jump conditional on status jcc rel (pc) (pc) + size (instr); if [cc] then (pc) (pc) + rel mnemon i c (1) comments binary mode (2) source mode (2) mnemonic , (1) comments bytes states bytes states jc rel jump if carry 2 1/4 (3) 2 1/4 (3) jnc rel jump if not carry 2 1/4 (3) 2 1/4 (3) je rel jump if equal 3 2/5 (3) 2 1/4 (3) jne rel jump if not equal 3 2/5 (3) 2 1/4 (3) jg rel jump if greater than 3 2/5 (3) 2 1/4 (3) jle rel jump if less than, or equal 3 2/5 (3) 2 1/4 (3) jsl rel jump if less than (signed) 3 2/5 (3) 2 1/4 (3) jsle rel jump if less than, or equal (signed) 3 2/5 (3) 2 1/4 (3) jsg rel jump if greater than (signed) 3 2/5 (3) 2 1/4 (3) jsge rel jump if greater than or equal (signed) 3 2/5 (3) 2 1/4 (3) notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. states are given as jump not-taken/taken. 3. in internal execution only, add 1 to the number of states of the `jump taken' if the destination address is internal and odd.
tsc80251g1d 26 rev. c october 14, 1998 table 32. summary of conditional jump instructions (2/2) jump if bit jb , rel (pc) (pc) + size (instr); if [src opnd= 1] then (pc) (pc) + rel jump if not bit jnb , rel (pc) (pc) + size (instr); if [src opnd= 0] then (pc) (pc) + rel jump if bit and clear jbc , rel (pc) (pc) + size (instr); if [dest opnd= 1] then dest opnd 0 (pc) (pc) + rel jump if accumulator is zero jz rel (pc) (pc) + size (instr); if [(a)= 0] then (pc) (pc) + rel jump if accumulator is not zero jnz rel (pc) (pc) + size (instr); if [(a) 0] then (pc) (pc) + rel compare and jump if not equal cjne , , rel (pc) (pc) + size (instr); if [src opnd1 < src opnd2] then (cy) 1 if [src opnd1 src opnd2] then (cy) 0 if [src opnd1 src opnd2] then (pc) (pc) + rel decrement and jump if not zero djnz , rel (pc) (pc) + size (instr); dest opnd dest opnd 1; if [ ? (z)] then (pc) (pc) + rel mnemon i c (1) comments binary mode (2) source mode (2) mnemonic , (1) comments bytes states bytes states jb bit51, rel jump if direct bit is set 3 2/5 (3)(6) 3 2/5 (3)(6) jb bit, rel jump if direct bit of 8-bit address location is set 5 4/7 (3)(6) 4 3/6 (3)(6) jnb bit51, rel jump if direct bit is not set 3 2/5 (3)(6) 3 2/5 (3)(6) jnb bit, rel jump if direct bit of 8-bit address location is not set 5 4/7 (3)(6) 4 3/6 (3) jbc bit51, rel jump if direct bit is set & clear bit 3 4/7 (5)(6) 3 4/7 (5)(6) jbc bit, rel jump if direct bit of 8-bit address location is set and clear 5 7/10 (5)(6) 4 6/9 (5)(6) jz rel jump if acc is zero 2 2/5 (6) 2 2/5 (6) jnz rel jump if acc is not zero 2 2/5 (6) 2 2/5 (6) a, dir8, rel compare direct address to acc and jump if not equal 3 2/5 (3)(6) 3 2/5 (3)(6) cjne a, #data, rel compare immediate to acc and jump if not equal 3 2/5 (6) 3 2/5 (6) cjne rn, #data, rel compare immediate to register and jump if not equal 3 2/5 (6) 4 3/6 (6) @ri, #data, rel compare immediate to indirect and jump if not equal 3 3/6 (6) 4 4/7 (6) djnz rn, rel decrement register and jump if not zero 2 2/5 (6) 3 3/6 (6) djnz dir8, rel decrement direct address and jump if not zero 3 3/6 (4)(6) 3 3/6 (4)(6) notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. states are given as jump not-taken/taken. 3. if this instruction addresses an i/o port (px, x= 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr . 4. if this instruction addresses an i/o port (px, x= 0-3), add 2 to the number of states. add 3 if it addresses a peripheral sfr . 5. if this instruction addresses an i/o port (px, x= 0-3), add 3 to the number of states. add 5 if it addresses a peripheral sfr . 6. in internal execution only, add 1 to the number of states of the `jump taken' if the destination address is internal and odd.
tsc80251g1d 27 rev. c october 14, 1998 table 33. summary of unconditional jump instructions absolute jump ajmp (pc) (pc) +2; (pc) 10:0 src opnd extended jump ejmp (pc) (pc) + size (instr); (pc) 23:0 src opnd long jump ljmp (pc) (pc) + size (instr); (pc) 15:0 src opnd short jump sjmp rel (pc) (pc) +2; (pc) (pc) +rel jump indirect jmp @a +dptr (pc) 23:16 ffh; (pc) 15:0 (a) + (dptr) no operation nop (pc) (pc) +1 mnemon i c (1) comments binary mode source mode mnemonic , (1) comments bytes states bytes states ajmp addr11 absolute jump 2 3 (2)(3) 2 3 (2)(3) ejmp addr24 extended jump 5 6 (2)(4) 4 5 (2)(4) ejmp @drk extended jump (indirect) 3 7 (2)(4) 2 6 (2)(4) ljmp @wrj long jump (indirect) 3 6 (2)(4) 2 5 (2)(4) ljmp addr16 long jump (direct address) 3 5 (2)(4) 3 5 (2)(4) sjmp rel short jump (relative address) 2 4 (2)(4) 2 4 (2)(4) jmp @a +dptr jump indirect relative to the dptr 1 5 (2)(4) 1 5 (2)(4) nop no operation (jump never) 1 1 1 1 notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. in internal execution only, add 1 to the number of states if the destination address is internal and odd. 3. add 2 to the number of states if the destination address is external. 4. add 3 to the number of states if the destination address is external. table 34. summary of call and return instructions absolute call acall (pc) (pc) +2; push (pc) 15:0 ; (pc) 10:0 src opnd extended call ecall (pc) (pc) + size (instr); push (pc) 23:0 ; (pc) 23:0 src opnd long call lcall (pc) (pc) + size (instr); push (pc) 15:0 ; (pc) 15:0 src opnd return from subroutine ret pop (pc) 15:0 extended return from subroutine eret pop (pc) 23:0 return from interrupt reti if [intr= 0] then pop (pc) 15:0 if [intr= 1] then pop (pc) 23:0 ; pop (psw1) trap interrupt trap (pc) (pc) + size (instr); if [intr= 0] then push (pc) 15:0 if [intr= 1] then push (psw1); push (pc) 23:0 mnemon i c (1) comments binary mode source mode mnemonic , (1) comments bytes states bytes states acall addr11 absolute subroutine call 2 9 (2)(3) 2 9 (2)(3) ecall @drk extended subroutine call (indirect) 3 14 (2)(3) 2 13 (2)(3) ecall addr24 extended subroutine call 5 14 (2)(3) 4 13 (2)(3) lcall @wrj long subroutine call (indirect) 3 10 (2)(3) 2 9 (2)(3) lcall addr16 long subroutine call 3 9 (2)(3) 3 9 (2)(3) ret return from subroutine 1 7 (2) 1 7 (2) eret extended subroutine return 3 9 (2) 2 8 (2) reti return from interrupt 1 7 (2)(4) 1 7 (2)(4) trap jump to the trap interrupt vector 2 12 (4) 1 11 (4) notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. in internal execution only, add 1 to the number of states if the destination/return address is internal and odd. 3. add 2 to the number of states if the destination address is external. 4. add 5 to the number of states if intr= 1.
tsc80251g1d 28 rev. c october 14, 1998 8. rom verifying 8.1. internal rom features mask rom devices the internal rom of the tsc83251g1d contains four different areas: code memory, configuration bytes, encryption array and signature bytes. all the internal rom of tsc83251g1d products is made of mask rom cells. they can be verified using the same algorithm as the eprom/otp devices. romless devices the tsc80251g1d products include only signature bytes made of mask rom cells. they can be verified using the same algorithm as the eprom/otp devices. these products do not include onchip configuration bytes, code memory and encryption array. 8.2. encryption features in some microcontrollers applications, it is desirable that the user program code be secured from unauthorized access. the tsc83251g1d products include a 128byte encryption array located in non volatile memory outside the memory address space. during verification of the onchip code memory, the seven loworder address bits also address the encryption array. as the byte of the code memory is read, it is exclusivenor'ed (xnor) with the key byte from the encryption array. if the encryption array is not programmed (still all 1s), the user program code is placed on the data bus in its original, unencrypted form. if the encryption array is programmed with key bytes, the user program code is encrypted and cannot be used without knowledge of the key byte sequence. note: when a movc instruction is executed the content of the rom is not encrypted. in order to fully protect the user program code, m ovc to the onchip code memory can only be executed from the onchip code memory when the encryption is used for mask rom devices. program code in the onchip code memory is encrypted when read out for verification if the encryption array is programmed. caution: if the encryption feature is implemented, the portion of the onchip code memory that does not contain program code should be f illed with arandomo byte values other than ffh to prevent the encryption key sequence from being revealed. to preserve the secrecy of the encryption key byte sequence, the encryption array cannot be verified. 8.3. signature bytes the tsc80251g1d derivatives contain factoryprogrammed signature bytes. these bytes are located in nonvolatile memory outside the memory address space at 30h, 31h, 60h and 61h. to read the signature bytes, perform the procedure described in paragraph averify algorithmo. the values of the signature bytes are listed in table 35. table 35. signature bytes (electronic id) signature address signature data vendor temic 30h 58h architecture c251 31h 40h memory 16k maskrom or romless 60h 7bh revision none (tsc80251g1 derivative) 61h ffh revision () first (tsc80251g1d derivative) 61h feh note: the way configuration bytes are used is changing from tsc80251g1 derivatives to tsc80251g1d derivatives. the verify algorithm s hould check the product revision to select the right model.
tsc80251g1d 29 rev. c october 14, 1998 8.4. verify algorithm figure 9 shows the hardware setup needed to verify the internal rom areas of the tsc80251g1d derivatives: the chip has to be put under reset and maintained in this state until the completion of the verify sequence. the voltage on the ea# pin has to be set to vdd. psen# and the other control signals (ale and port 0) have to be set to a logic high level. then psen# has to be to forced to a logic low level after two clock cycles or more and it has to be maintained in this state until the completion of the programming sequence. the verify mode is selected according to the code applied on port 0 (see table 36). it has to be applied until the completion of this verification. the verification address is applied on ports 1 and 3 which are respectively the msb and the lsb of the address. then device is driving the data on port 2. psen# and the other control signals have to be released to complete a sequence of verify operations. table 36. verifying modes verify rom rst ea# psen# ale p0 p2 p1(msb) p3(lsb) onchip code memory 1 1 0 1 28h data 16bit address: 0000h-3fffh (16k) configuration bytes 1 1 0 1 29h data uconfig0: fff8h uconfig1: fff9h signature bytes 1 1 0 1 29h data 30h, 31h, 60h, 61h ale rst ea# psen# vdd p1[7:0] p3[7:0] vss p0[7:0] a[15:8] a[7:0] mode vdd tsc80251g1d vdd data xtal1 p2[7:0] 4 to 12 mhz vss1 vss2 figure 9. setup for rom verifying
tsc80251g1d 30 rev. c october 14, 1998 9. absolute maximum rating and operating conditions 9.1. absolute maximum rating table 37. absolute maximum ratings storage temperature . . . . . . . . . . . . . . . . . . . . voltage on any other pin to vss . . . . . . . . . . . i ol per i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation . . . . . . . . . . . . . . . . . . . . . . 65 to +150 c 0.5 to +6.5 v 15 ma 1.5 w 9.2. operating conditions table 38. operating conditions ambient temperature under bias commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dd high speed versions . . . . . . . . . . . . . . . . . . . . . low voltage versions . . . . . . . . . . . . . . . . . . . . 0 to +70 c 40 to +85 c 4.5 to 5.5 v 2.7 to 5.5 v note: stressing the device beyond the aabsolute maximum ratingso may cause permanent damage. these are stress ratings only. operation beyond the aoperating conditionso is not recommended and extended exposure beyond the aoperating conditionso may affect device reliability .
tsc80251g1d 31 rev. c october 14, 1998 10. dc characteristics commercial & industrial 10.1. dc characteristics: high speed versions commercial & industrial table 39. dc characteristics; v dd = 4.5 to 5.5 v, t a = 40 to +85 c symbol parameter min typical (4) max units test conditions v il input low voltage (except ea#, scl, sda) 0.5 0.2v dd - 0.1 v v il1 (5) input low voltage (scl, sda) 0.5 0.3v dd v v il2 input low voltage (ea#) 0 0.2v dd - 0.3 v v ih input high voltage (except xtal1, rst, scl, sda) 0.2v dd + 0.9 v dd + 0.5 v v ih1 (5) input high voltage (xtal1, rst, scl, sda) 0.7v dd v dd + 0.5 v v ol output low voltage (ports 1, 2, 3) 0.3 0.45 1.0 v i ol = 100 m a (1)(2) i ol = 1.6 ma (1)(2) i ol = 3.5 ma (1)(2) v ol1 output low voltage (ports 0, ale, psen#,port 2 in page mode during external address) 0.3 0.45 1.0 v i ol = 200 m a (1)(2) i ol = 3.2 ma (1)(2) i ol = 7.0 ma (1)(2) v oh output high voltage (ports 1, 2, 3, ale, psen#) v dd 0.3 v dd 0.7 v dd 1.5 v i oh = 10 m a (3) i oh = 30 m a (3) i oh = 60 m a (3) v oh1 output high voltage (port 0, port 2 in page mode during external address) v dd 0.3 v dd 0.7 v dd 1.5 v i oh = 200 m a i oh = 3.2 ma i oh = 7.0 ma v rst + reset threshold on 3.9 4.1 4.3 v v rst reset threshold off 3.4 3.6 3.8 v v ret v dd data retention limit 1.8 v i il0 logical 0 input current (ports 1, 2, 3) - 50 m a v in = 0.45 v i il1 logical 1 input current (nmi) + 50 m a v in = v dd i li input leakage current (port 0) 10 m a 0.45 v < v in < v dd i tl logical 1-to-0 transition current (ports 1, 2, 3 await#) - 650 m a v in = 2.0 v r rst rst pulldown resistor 40 170 225 k c io pin capacitance 10 pf t a = 25 c 18 25 ma f osc = 12 mhz i dd operating current 23 30 ma f osc = 16 mhz dd pg 34 40 ma f osc = 24 mhz 5 6 ma f osc = 12 mhz i dl idle mode current 6.5 8 ma f osc = 16 mhz dl 9.5 12 ma f osc = 24 mhz i pd powerdown current 2 20 m a v ret < v dd < 5.5 v
tsc80251g1d 32 rev. c october 14, 1998 notes: 1. under steadystate (nontransient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma . . . . . . . . . . . . . . . . . . . . . . . maximum i ol per 8bit port: port 0 26 ma . . . . . . . ports 1-3 15 ma . . . . . maximum total i ol for all: output pins 71 ma . . . if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the lowlevel outputs of ale and ports 1, 2, and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. in applica tions where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or ot her signals with a schmitt trigger or cmoslevel input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen# to drop below the specification when the address lines are stabilizing. 4. typical values are obtained using v dd = 5 v and t a = 25 c with no guarantee. they are not tested and there is not guarantee on these values. 5. the input threshold voltage of scl and sda meets the i 2 c specification, so an input voltage below 0.3.v dd will be recognized as a logic 0 while an input voltage above 0.7.v dd will be recognized as a logic 1. 24 0 40 30 20 10 12 14 16 18 20 22 6 4 2810 frequency at xtal (1) (mhz) i dd /i dl (ma) max active mode (ma) typ active mode (ma) max idle mode (ma) typ idle mode (ma) note: 1. the clock prescaler is not used: f osc = f xtal . figure 10. i dd /i dl versus frequency; v dd = 4.5 to 5.5 v
tsc80251g1d 33 rev. c october 14, 1998 10.2. dc characteristics: low voltage versions commercial & industrial table 40. dc characteristics from 2.7 to 5.5 v, t a = 40 to +85 c symbol parameter min typical (4) max units test conditions v il input low voltage (except ea#, scl, sda) 0.5 0.2v dd - 0.1 v v il1 (5) input low voltage (scl, sda) 0.5 0.3v dd v v il2 input low voltage (ea#) 0 0.2v dd - 0.3 v v ih input high voltage (except xtal1, rst, scl, sda) 0.2v dd + 0.9 v dd + 0.5 v v ih1 (5) input high voltage (xtal1, rst, scl, sda) 0.7v dd v dd + 0.5 v v ol output low voltage (ports 1, 2, 3) 0.45 v i ol = 0.8 ma (1)(2) v ol1 output low voltage (ports 0, ale, psen#,port 2 in page mode during external address) 0.45 v i ol = 1.6 ma (1)(2) v oh output high voltage (ports 1, 2, 3, ale, psen#) 0.9v dd v i oh = 10 m a (3) v oh1 output high voltage (port 0, port 2 in page mode during external address) 0.9v dd v i oh = 40 m a v rst + reset threshold on 2.1 2.3 2.4 v v rst reset threshold off 1.8 2.0 2.1 v v ret v dd data retention limit 1.8 v i il0 logical 0 input current (ports 1, 2, 3 await#) - 50 m a v in = 0.45 v i il1 logical 1 input current (nmi) + 50 m a v in = v dd i li input leakage current (port 0) 10 m a 0.45 v < v in < v dd i tl logical 1-to-0 transition current (ports 1, 2, 3) - 650 m a v in = 2.0 v r rst rst pulldown resistor 40 170 225 k c io pin capacitance 10 pf t a = 25 c 3.5 8 ma 5 mhz, v dd < 3.6 v i dd operating current 7 11 ma 10 mhz, v dd < 3.6v 8 13 ma 12 mhz, v dd < 3.6 v 0.5 1 ma 5 mhz, v dd < 3.6 v i dl idle mode current 1.5 4 ma 10 mhz, v dd < 3.6 v 2 5 ma 12 mhz, v dd < 3.6 v i pd powerdown current 2 10 m a v ret < v dd < 3.6 v
tsc80251g1d 34 rev. c october 14, 1998 notes: 1. under steadystate (nontransient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma . . . . . . . . . . . . . . . . . . . . . . . maximum i ol per 8bit port: port 0 26 ma . . . . . . . ports 1-3 15 ma . . . . . maximum total i ol for all: output pins 71 ma . . . if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the lowlevel outputs of ale and ports 1, 2, and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. i n applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmoslevel input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen# to drop below the specification when the address lines are stabilizing. 4. typical values are obtained using v dd = 3 v and t a = 25 c with no guarantee. they are not tested and there is not guarantee on these values. 5.the input threshold voltage of scl and sda meets the i 2 c specification, so an input voltage below 0.3.v dd will be recognized as a logic 0 while an input voltage above 0.7.v dd will be recognized as a logic 1. 12 0 10 15 5 67 8 91011 3 2 145 frequency at x tal (1) (mhz) i dd /i dl (ma) max active mode (ma) typ active mode (ma) max idle mode (ma) typ idle mode (ma) note: 1. the clock prescaler is not used: f osc = f xtal . figure 11. i dd /i dl versus x tal frequency; v dd = 2.7 to 5.5 v
tsc80251g1d 35 rev. c october 14, 1998 10.3. dc characteristics: i dd, i dl and i pd test conditions xtal2 xtal1 vss vdd ea# p0 tsc80251g1d vdd rst i dd (nc) all other pins are unconnected vdd clock signal vdd figure 12. i dd test condition, active mode xtal2 xtal1 vss vdd ea# p0 tsc80251g1d vdd rst i dl (nc) all other pins are unconnected vdd clock signal figure 13. i dl test condition, idle mode xtal2 xtal1 vss vdd ea# p0 tsc80251g1d vdd rst i pd (nc) all other pins are unconnected vdd figure 14. i pd test condition, powerdown mode
tsc80251g1d 36 rev. c october 14, 1998 11. ac characteristics commercial & industrial 11.1. ac characteristics external bus cycles definition of symbols table 41. external bus cycles timing symbol definitions signals conditions a address h high d data in l low l ale v valid q data out x no longer valid r rd#/psen# z floating w wr# timings test conditions: capacitive load on all pins= 50 pf. table 42 and table 43 list ac timing parameters for the tsc80251g1d with no wait states. external wait states can be added by extending psen#/rd#/wr# and or by extending ale. in these tables, note 2 marks parameters affected by one ale wait state, and note 3 marks parameters affected by psen#/rd#/wr# wait states. figure 15 to figure 20 show the bus cycles with the timing parameters.
tsc80251g1d 37 rev. c october 14, 1998 table 42. bus cycles ac timings; v dd = 4.5 to 5.5 v, t a = 40 to 85 c symbol parameter 12 mhz 16 mhz 24 mhz un i t symbol parameter min max min max min max unit t osc 1/f osc 83 62 41 ns t lhll ale pulse width 82 61 40 ns (2) t av l l address valid to ale low 80 59 38 ns (2) t llax address hold after ale low 27 19 2.5 ns t rlrh (1) rd#/psen# pulse width 158 118 76 ns (3) t wlwh wr# pulse width 160 120 78 ns (3) t llrl (1) ale low to rd#/psen# low 41 27 14 ns t lhax ale high to address hold 116 81 43 ns (2) t rldv (1) rd#/psen# low to valid data 144 102 59 ns (3) t rhdx (1) data hold after rd#/psen# high 0 0 0 ns t rhax (1) address hold after rd#/psen# high 0 0 0 ns t rlaz (1) rd#/psen# low to address float 2 2 2 ns t rhdz1 instruction float after rd#/psen# high 23 23 23 ns t rhdz2 data float after rd#/psen# high 188 146 104 ns t rhlh1 rd#/psen# high to ale high (instruction) 24 24 24 ns t rhlh2 rd#/psen# high to ale high (data) 189 148 104 ns t whlh wr# high to ale high 192 150 103 ns t avdv1 address (p0) valid to valid data in 262 187 110 ns (2)(3) t avdv2 address (p2) valid to valid data in 300 217 137 ns (2)(3) t avdv3 address (p0) valid to valid instruction in 146 104 62 ns t axdx data hold after address hold 0 0 0 ns t av r l (1) address valid to rd# low 125 91 57 ns (2) t av w l 1 address (p0) valid to wr# low 124 90 53 ns (2) t av w l 2 address (p2) valid to wr# low 162 119 75 ns (2) t whqx data hold after wr# high 81 60 37 ns t qvwh data valid to wr# high 135 104 74 ns (3) t whax wr# high to address hold 168 126 84 ns notes: 1. specification for psen# are identical to those for rd#. 2. if a wait state is added by extending ale, add 2 t osc. 3. if wait states are added by extending rd#/psen#/wr#, add 2n t osc (n= 1..3).
tsc80251g1d 38 rev. c october 14, 1998 table 43. bus cycles ac timings; v dd = 2.7 to 5.5 v, t a = 40 to 85 c symbol parameter 12 mhz un i t symbol parameter min max unit t osc 1/f osc 83 ns t lhll ale pulse width 81 ns (2) t av l l address valid to ale low 66 ns (2) t llax address hold after ale low 5 ns t rlrh (1) rd#/psen# pulse width 152 ns (3) t wlwh wr# pulse width 155 ns (3) t llrl (1) ale low to rd#/psen# low 34 ns t lhax ale high to address hold 93 ns (2) t rldv (1) rd#/psen# low to valid data 115 ns (3) t rhdx (1) data hold after rd#/psen# high 0 ns t rhax (1) address hold after rd#/psen# high 0 ns t rlaz (1) rd#/psen# low to address float 2 (4) ns t rhdz1 instruction float after rd#/psen# high 35 ns t rhdz2 data float after rd#/psen# high 199 ns t rhlh1 rd#/psen# high to ale high (instruction) 24 ns t rhlh2 rd#/psen# high to ale high (data) 189 ns t whlh wr# high to ale high 192 ns t avdv1 address (p0) valid to valid data in 214 ns (2)(3) t avdv2 address (p2) valid to valid data in 271 ns (2)(3) t avdv3 address (p0) valid to valid instruction in 131 ns t axdx data hold after address hold 0 ns t av r l (1) address valid to rd# low 114 ns (2) t av w l 1 address (p0) valid to wr# low 112 ns (2) t av w l 2 address (p2) valid to wr# low 161 ns (2) t whqx data hold after wr# high 87 ns t qvwh data valid to wr# high 135 n (3) t whax wr# high to address hold 164 ns notes: 1. specification for psen# are identical to those for rd#. 2. if a wait state is added by extending ale, add 2 t osc. 3. if wait states are added by extending rd#/psen#/wr#, add 2n t osc (n= 1..3). 4. t rlaz max is 0 ns if v dd < 3.6v.
tsc80251g1d 39 rev. c october 14, 1998 waveforms in nonpage mode instruction in t rhlh1 t rlrh (1) t llrl (1) t lhll (1) t rldv (1) t rlaz t av l l (1) t llax t rhdx t rhdz1 t av r l (1) t avdv1 (1) t avdv2 (1) p2/a16/a17 p0 rd#/psen# ale a15:8/a16/a17 t lhax (1) d7:0 a7:0 t rhax note: 1. the value of this parameter depends on wait states. see table 42 and table 43. figure 15. external bus cycle: code fetch (nonpage mode) t rhlh2 t rlrh (1) t llrl (1) t lhll (1) t rldv (1) t rlaz t av l l (1) t llax t rhdx t rhdz2 t av r l (1) t avdv1 (1) t avdv2 (1) p2/a16/a17 p0 rd#/psen# ale a15:8/a16/a17 t lhax (1) d7:0 a7:0 data in t rhax note: 1. the value of this parameter depends on wait states. see table 42 and table 43. figure 16. external bus cycle: data read (nonpage mode)
tsc80251g1d 40 rev. c october 14, 1998 t whlh t wlwh (1) t lhll (1) t av l l (1) t llax t av w l 1 (1) t av w l 2 (1) p2/a16/a17 p0 wr# ale a15:8/a16/a17 t lhax (1) d7:0 t qvwh a7:0 t whax t whqx data out note: 1. the value of this parameter depends on wait states. see table 42 and table 43. figure 17. external bus cycle: datawrite (nonpage mode) waveforms in page mode t llrl (1) t lhll (1) t rldv (1) t rlaz t av l l (1) t llax t rhdx t rhdz1 t av r l (1) t av d v 1 (1) a7:0/a16/a17 t lhax (1) d7:0 a15:8 d7:0 page miss (2) page hit (2) t avdv3 (1) p0/a16/a17 p2 rd#/psen# (3) ale a7:0/a16/a17 t av d v 2 (1) t rhax instruction in t axdx instruction in notes: 1. the value of this parameter depends on wait states. see table 42 and table 43. 2. a page hit (i.e., a code fetch to the same 256-byte apageo as the previous code fetch) requires one state (2 t osc );a page miss requires two states (4 t osc ). 3. during a sequence of page hits, psen# remains low until the end of the last pagehit cycle. figure 18. external bus cycle: code fetch (page mode)
tsc80251g1d 41 rev. c october 14, 1998 t rhlh2 t rlrh (1) t llrl (1) t lhll (1) t rldv (1) t rlaz t av l l (1) t llax t rhdx t rhdz2 t av r l (1) t avdv1 (1) t avdv2 (1) p0/a16/a17 p2 rd#/psen# ale a15:8/a16/a17 t lhax (1) d7:0 a7:0 data in t rhax note: 1. the value of this parameter depends on wait states. see table 42 and table 43. figure 19. external bus cycle: data read (page mode) t whlh t wlwh (1) t lhll (1) t av l l (1) t llax t av w l 1 (1) t av w l 2 (1) p0/a16/a17 p2 wr# ale a15:8/a16/a17 t lhax (1) d7:0 t qvwh a7:0 t whax t whqx data out note: 1. the value of this parameter depends on wait states. see table 42 and table 43. figure 20. external bus cycle: datawrite (page mode)
tsc80251g1d 42 rev. c october 14, 1998 11.2. ac characteristics realtime synchronous wait state definition of symbols table 44. realtime synchronous wait timing symbol definitions signals conditions c wclk l low r rd#/psen# v valid w wr# x no longer valid y wait# timings table 45. realtime synchronous wait ac timings; v dd = 2.7 to 5.5 v, t a = 40 to 85 c symbol parameter min max unit t clyv wait clock low to wait setup 0 t osc 20 ns t clyx wait hold after wait clock low 2w t osc + 5 (1+2w) t osc 20 ns t rlyv psen#/rd# low to wait setup 0 t osc 20 ns t rlyx wait hold after psen#/rd# low 2w t osc + 5 (1+2w) t osc 20 ns t wlyv wr# low to wait setup 0 t osc 20 ns t wlyx wait hold after wr# low 2w t osc + 5 (1+2w) t osc 20 ns waveforms wclk ale rd#/psen# p0 p2 state 1 state 2 state 3 state 1 (next cycle) wait# t rlyx max t rlyx min t rlyv t clyv t clyx min t clyx max rd#/psen# stretched a15:8 d7:0 a7:0 stretched stretched a15:8 a7:0 figure 21. realtime synchronous wait state: code fetch/data read
tsc80251g1d 43 rev. c october 14, 1998 wclk ale wr# p0 p2 state 1 a15:8 d7:0 state 2 state 3 state 4 stretched stretched wait# a7:0 wr# stretched t wlyx max t wlyx min t wlyv t clyv t clyx min t clyx max figure 22. realtime synchronous wait state: data write 11.3. ac characteristics realtime asynchronous wait state definition of symbols table 46. realtime asynchronous wait timing symbol definitions signals conditions s psen#/rd#/wr# l low y await# v valid x no longer valid timings table 47. realtime asynchronous wait ac timings; v dd = 2.7 to 5.5 v, t a = 40 to 85 c symbol parameter min max unit t slyv psen#/rd#/wr# low to wait setup t osc 10 ns t slyx wait hold after psen#/rd#/wr# low (2n1) t osc + 10 ns (1) note: 1. n is the number of wait states added (n 1). waveforms rd#/psen#/wr# t slyv await# t slyx figure 23. realtime asynchronous wait state timings
tsc80251g1d 44 rev. c october 14, 1998 11.4. ac characteristics serial port in shift register mode definition of symbols table 48. serial port timing symbol definitions signals conditions d data in h high q data out l low x clock v valid x no longer valid timings table 49. serial port ac timing shift register mode; v dd = 2.7 to 5.5 v, t a = 40 to 85 c symbol parameter 12 mhz 16 mhz (1) 24 mhz (1) un i t symbol parameter min max min max min max unit t xlxl serial port clock cycle time 998 749 500 ns t qvxh output data setup to clock rising edge 833 625 417 ns t xhqx output data hold after clock rising edge 165 124 82 ns t xhdx input data hold after clock rising edge 0 0 0 ns t xhdv clock rising edge to input data valid 974 732 482 ns note: 1. for high speed versions only. waveforms valid valid valid valid valid valid valid valid 01 23 45 6 7 t xlxl t xhdv t xhdx t qvxh t xhqx set ti (1) set ri (1) txd rxd (out) rxd (in) note: 1. ti and ri are set during s1p1 of the peripheral cycle following the shift of the eight bit. figure 24. serial port waveforms shift register mode
tsc80251g1d 45 rev. c october 14, 1998 11.5. ac characteristics sslc: i 2 c interface timings table 50. i 2 c interface ac timing; v dd = 2.7 to 5.5 v, t a = 40 to 85 c symbol parameter input min max output min max t hd; sta start condition hold time 14 t clcl (4) 4.0 m s (1) t low scl low time 16 t clcl (4) 4.7 m s (1) t high scl high time 14 t clcl (4) 4.0 m s (1) t rc scl rise time 1 m s (2) t fc scl fall time 0.3 m s 0.3 m s (3) t su; dat 1 data setup time 250 ns 20 t clcl (4) t rd t su; dat 2 sda setup time (before repeated start condition) 250 ns 1 m s (1) t su; dat 3 sda setup time (before stop condition) 250 ns 8 t clcl (4) t hd; dat data hold time 0 ns 8 t clcl (4) t fc t su; sta repeated start setup time 14 t clcl (4) 4.7 m s (1) t su; sto stop condition setup time 14 t clcl (4) 4.0 m s (1) t buf bus free time 14 t clcl (4) 4.7 m s (1) t rd sda rise time 1 m s (2) t fd sda fall time 0.3 m s 0.3 m s (3) notes: 1. at 100 kbit/s. at other bitrates this value is inversely proportional to the bitrate of 100 kbit/s. 2. determined by the external busline capacitance and the external busline pullup resistor, this must be < 1 m s. 3. spikes on the sda and scl lines with a duration of less than 3 t clcl will be filtered out. maximum capacitance on buslines sda and scl= 400 pf. 4. t clcl = t osc = one oscillator clock period. waveforms start or repeated start condition repeated start condition stop condition start condition sda (input/output) scl (input/output) 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd t su ;sta t su ;sto t buf t high t rd t rc t su ;dat3 t fc t fd t low t su ;dat2 t su ;dat1 t hd ;dat t hd ;sta figure 25. i 2 c waveforms
tsc80251g1d 46 rev. c october 14, 1998 11.6. ac characteristics sslc: spi interface definition of symbols table 51. spi interface timing symbol definitions signals conditions c clock h high i data in l low o data out v valid s ss# x no longer valid z floating timings table 52. spi interface ac timing; v dd = 2.7 to 5.5 v, t a = 40 to 85 c symbol parameter min max unit slave mode (1) t chch clock period 8 t osc t chcx clock high time 3.2 t osc t clcx clock low time 3.2 t osc t slch , t slcl ss# low to clock edge 200 ns t ivcl , t ivch input data valid to clock edge 100 ns t clix , t chix input data hold after clock edge 100 ns t clov , t chov output data valid after clock edge 100 ns t clox , t chox output data hold time after clock edge 0 ns t clsh , t chsh ss# high after clock edge 0 ns t ivcl , t ivch input data valid to clock edge 100 ns t clix , t chix input data hold after clock edge 100 ns t slov ss# low to output data valid 130 ns t shox output data hold after ss# high 130 ns t shsl ss# high to ss# low (2) t ilih input rise time 2 m s t ihil input fall time 2 m s t oloh output rise time 100 ns t ohol output fall time 100 ns
tsc80251g1d 47 rev. c october 14, 1998 symbol parameter min max unit master mode (3) t chch clock period 4 t osc t chcx clock high time 1.6 t osc t clcx clock low time 1.6 t osc t ivcl , t ivch input data valid to clock edge 50 ns t clix , t chix input data hold after clock edge 50 ns t clov , t chov output data valid after clock edge 65 ns t clox , t chox output data hold time after clock edge 0 ns t ilih input data rise time 2 m s t ihil input data fall time 2 m s t oloh output data rise time 50 ns t ohol output data fall time 50 ns notes: 1. capacitive load on all pins= 200 pf in slave mode. 2. the value of this parameter depends on software. 3. capacitive load on all pins= 100 pf in master mode. waveforms miso (input) sck (sscpol=0) (output) ss# (1) (output) sck (sscpol=1) (output) msb in bit 6 lsb in mosi (output) msb out lsb out t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox port data port data bit 6 note: 1. ss# handled by software. figure 26. spi master waveforms (sscpha= 0)
tsc80251g1d 48 rev. c october 14, 1998 miso (input) sck (sscpol=0) (output) ss# (1) (output) sck (sscpol=1) (output) msb in bit 6 lsb in mosi (output) msb out lsb out t chch t ivcl t clix t chix t ivch t clov t chov t clox t chox t chcl t clch port data port data bit 6 t clcx t chcx note: 1. ss# handled by software. figure 27. spi master waveforms (sscpha= 1) t ivcl t clix t chix t ivch mosi (input) sck (sscpol=0) (input) ss# (input) sck (sscpol=1) (input) msb in bit 6 lsb in miso (output) slave msb out slave lsb out bit 6 (1) t slcl t slch t chch t chcl t clch t chov t clov t slov t chox t clox t shox t shsl t chsh t clsh t clcx t chcx note: 1. not defined but normally msb of character just received. figure 28. spi slave waveforms (sscpha= 0)
tsc80251g1d 49 rev. c october 14, 1998 t ivcl t clix t chix t ivch mosi (input) sck (sscpol=0) (input) ss# (input) sck (sscpol=1) (input) msb in bit 6 lsb in miso (output) slave msb out slave lsb out bit 6 (1) t slcl t slch t chch t chcl t clch t clov t chov t slov t clox t chox t shox t shsl t chsh t clsh note: 1. not defined but generally the lsb of the character which has just been received. figure 29. spi slave waveforms (sscpha= 1)
tsc80251g1d 50 rev. c october 14, 1998 11.7. ac characteristics rom verifying definition of symbols table 53. rom verifying timing symbol definitions signals conditions a address h high e enable: mode set on port 0 l low q data out v valid x no longer valid z floating timings table 54. rom verifying ac timings; v dd = 4.5 to 5.5 v, t a = 0 to 40 c symbol parameter min max unit t osc xtal1 frequency 82.5 250 ns t avqv address to data valid 48 t osc ns t axqx address to data invalid 0 ns t elqv enable low to data valid 0 48 t osc ns t ehqz data float after enable 0 48 t osc ns waveforms t elqv t ehqz address data t avqv p1= a15:8 p3= a7:0 p2= d7:0 p0 mode= 28h, 29h or 2bh t axqx figure 30. rom verifying waveforms
tsc80251g1d 51 rev. c october 14, 1998 11.8. ac characteristics external clock drive and logic level references definition of symbols table 55. external clock timing symbol definitions signals conditions c clock l low h high x no longer valid timings table 56. external clock ac timings; v dd = 4.5 to 5.5 v, t a = 40 to +85 c symbol parameter min max unit f osc oscillator frequency 24 mhz t chcx high time 10 ns t clcx low time 10 ns t clch rise time 3 ns t chcl fall time 3 ns waveforms 0.45 v t clcl v dd 0.5 v ih1 v il t chcx t clch t chcl t clcx figure 31. external clock waveform 0.45 v v dd 0.5 0.2 v dd + 0.9 0.2 v dd 0.1 v ih min v il max inputs outputs note: during ac testing, all inputs are driven at v dd 0.5 v for a logic 1 and 0.45 v for a logic 0. timing measurements are made on all outputs at v ih min for a logic 1 and v il max for a logic 0. figure 32. ac testing input/output waveforms v load v oh 0.1 v v ol + 0.1 v v load + 0.1 v v load 0.1 v timing reference points note: for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol /i oh = 20 ma. figure 33. float waveforms
tsc80251g1d 52 rev. c october 14, 1998 12. packages 12.1. list of packages pdil 40 plcc 44 vqfp 44 (10 10) 12.2. pdil 40 mechanical outline figure 34. plastic dual in line table 57. pdil package size mm inch min max min max a 5.08 .200 a1 0.38 .015 a2 3.18 4.95 .125 .195 b 0.36 0.56 .014 .022 b1 0.76 1.78 .030 .070 c 0.20 0.38 .008 .015 d 50.29 53.21 1.980 2.095 e 15.24 15.87 .600 .625 e1 12.32 14.73 .485 .580 e 2.54 b.s.c. .100 b.s.c. ea 15.24 b.s.c. .600 b.s.c. eb 17.78 .700 l 2.93 3.81 .115 .150 d1 0.13 .005
tsc80251g1d 53 rev. c october 14, 1998 12.3. plcc 44 mechanical outline figure 35. plastic lead chip carrier table 58. plcc package size mm inch min max min max a 4.20 4.57 .165 .180 a1 2.29 3.04 .090 .120 d 17.40 17.65 .685 .695 d1 16.44 16.66 .647 .656 d2 14.99 16.00 .590 .630 e 17.40 17.65 .685 .695 e1 16.44 16.66 .647 .656 e2 14.99 16.00 .590 .630 e 1.27 bsc .050 bsc g 1.07 1.22 .042 .048 h 1.07 1.42 .042 .056 j 0.51 .020 k 0.33 0.53 .013 .021 nd 11 11 ne 11 11
tsc80251g1d 54 rev. c october 14, 1998 12.4. vqfp 44 (10 10) mechanical outline figure 36. shrink quad flat pack (plastic) table 59. vqfp package size mm inch min max min max a 1.60 .063 a1 0.64 ref .025 ref a2 0.64 ref .025ref a3 1.35 1.45 .053 .057 d 11.90 12.10 .468 .476 d1 9.90 10.10 .390 .398 e 11.90 12.10 .468 .476 e1 9.90 10.10 .390 .398 j 0.05 .002 6 l 0.45 0.75 .018 .030 e 0.80 bsc .0315 bsc f 0.35 bsc .014 bsc
tsc80251g1d 55 rev. c october 14, 1998 13. ordering information 13.1. tsc80251g1d romless (step d) high speed versions 4.5 to 5.5 v, commercial and industrial temic part number (2) rom description tsc80251g1d24ca romless 24 mhz, commercial 0 to 70 c, pdil 40 tsc80251g1d24cb romless 24 mhz, commercial 0 to 70 c, plcc 44 tsc80251g1d24ced romless 24 mhz, commercial 0 to 70 c, vqfp 44, dry pack (1) tsc80251g1d16ca romless 16 mhz, commercial 0 to 70 c, pdil 40 tsc80251g1d16cb romless 16 mhz, commercial 0 to 70 c, plcc 44 tsc80251g1d16ced romless 16 mhz, commercial 0 to 70 c, vqfp 44, dry pack (1) tsc80251g1d16ia romless 16 mhz, industrial 40 to 85 c, pdil 40 tsc80251g1d16ib romless 16 mhz, industrial 40 to 85 c, plcc 44 low voltage versions 2.7 to 5.5 v, commercial temic part number (2) rom description tsc80251g1dl12cb romless 12 mhz, commercial, plcc 44 tsc80251g1dl12ced romless 12 mhz, commercial, vqfp 44, dry pack (1) 13.2. tsc83251g1d mask rom (step d) high speed versions 4.5 to 5.5 v, commercial and industrial temic part number (2) rom description tsc251g1dxxx24ca 16k maskrom 24 mhz, commercial 0 to 70 c, pdil 40 tsc251g1dxxx24cb 16k maskrom 24 mhz, commercial 0 to 70 c, plcc 44 tsc251g1dxxx24ced 16k maskrom 24 mhz, commercial 0 to 70 c, vqfp 44, dry pack (1) tsc251g1dxxx16ca 16k maskrom 16 mhz, commercial 0 to 70 c, pdil 40 tsc251g1dxxx16cb 16k maskrom 16 mhz, commercial 0 to 70 c, plcc 44 tsc251g1dxxx16ced 16k maskrom 16 mhz, commercial 0 to 70 c, vqfp 44, dry pack (1) tsc251g1dxxx16ia 16k maskrom 16 mhz, industrial 40 to 85 c, pdil 40 tsc251g1dxxx16ib 16k maskrom 16 mhz, industrial 40 to 85 c, plcc 44 low voltage versions 2.7 to 5.5 v, commercial temic part number (2) rom description tsc251g1dxxxl12cb 16k maskrom 12 mhz, commercial 0 to 70 c, plcc 44 tsc251g1dxxxl12ced 16k maskrom 12 mhz, commercial 0 to 70 c, vqfp 44, dry pack (1) notes: 1. dry pack mandatory for vqfp package. 2. xxx: means rom code, is cxxx in case of encrypted code.
tsc80251g1d 56 rev. c october 14, 1998 13.3. tsc87251g1a otp (step a) high speed versions 4.5 to 5.5 v, commercial and industrial temic part number rom description tsc87251g1a16ca 16k otp rom 16 mhz, commercial 0 to 70 c, pdil 40 tsc87251g1a16cb 16k otp rom 16 mhz, commercial 0 to 70 c, plcc 44 tsc87251g1a16ia 16k otp rom 16 mhz, industrial 40 to 85 c, pdil 40 tsc87251g1a16ib 16k otp rom 16 mhz, industrial 40 to 85 c, plcc 44 13.4. tsc87251g1a eprom uv window package (step a) high speed versions 4.5 to 5.5 v, industrial temic part number rom description tsc87251g1a16ic 16k eprom 16 mhz, industrial 40 to 85 c, window cqpj 44 13.5. options (please consult temic sales) rom code encryption tape & real or dry pack known good dice ceramic packages extended temperature range: 55 c to +125 c 13.6. starter kit temic part number description tsc80251sk tsc80251 starter kit 13.7. product marking mask rom versions temic temic part number ? intel'97 yyww . lot number romless versions temic temic part number ? intel'95 yyww . lot number otp versions temic customer part number temic part number ? intel'97 yyww . lot number

▲Up To Search▲

Price & Availability of TSC80251G1D-L12CB

	To Download TSC80251G1D-L12CB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .